Field effect transistor with reduced delay variation

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

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257192, 257408, H01L 310328, H01L 2900, H01L 2976

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active

059427736

ABSTRACT:
A field effect transistor with a reduced delay variation is provided in a compound semiconductor layer with a channel, a source, and a drain region of a first conduction type. A gate electrode, a source electrode, and a drain electrode are formed respectively on the regions mentioned above. Particularly the gate electrode formed on the channel is provided with a projecting part extended in a direction crossing the direction of opposition of the source and drain region and caused to protrude from the channel region. In the compound semiconductor layer, a well region of a second conduction type opposite to the first conduction type is formed so as to enclose the channel region, the source region, the drain region, and the projecting part of the gate electrode more deeply than in the channel, source, and drain regions. The delay variation is markedly reduced by the fact that the gate electrode including the projecting part is enclosed with the well region of the second conduction type.

REFERENCES:
patent: 5324969 (1994-06-01), Murai et al.
Kimura et al., "Schottky Characteristics of Subhalf-Micron Gate Gaas Metal-Semiconductor Field-Effect Transistor", Japanese Journal of Applied Physics, vol. 32, No. 2A, Part 2, Feb. 1, 1993, pp. L183-L186.
"A -p-Well GaAs MESFET Technology for Mixed-Mode Applications," Canfield et al., IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1544-1549.
"Elimination of Sidegating in N-Channel GaAs MESFET's Using a P-Type Well.sup.1," Canfield et al., GaAs IC Symposium, pp. 237-240.
"Trap Effects in p-Channel GaAs MESFET's," Peng et al., IEEE Transactions on Electron Devices, vol. 39, No. 11, Nov. 1992, pp. 2444-2451.

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