Semiconductor memory device having redundancy configuration with

Details Semiconductor memory device having redundancy configuration with Semiconductor memory device having redundancy configuration with

1986-07-09

1988-11-08

Smith, Jerry

Excavating

365200, G06F 1120

Patent

active

047837810

ABSTRACT:
A semiconductor memory device having a redundancy configuration including a read circuit for a defective memory address. The read circuit includes a transistor which forms a current switch circuit with a bipolar-transistor of an input buffer circuit. The base electrode of the transistor is connected to the output terminal of a PROM which stores a defective address. The reading operation is carried out by applying a voltage lower than a normally applied voltage to the base electrode of the bipolar-transistor and detecting the base current.

REFERENCES:
patent: 4583179 (1986-04-01), Horii
patent: 4592024 (1986-05-01), Sakai
patent: 4635232 (1987-01-01), Iwahashi
patent: 4656609 (1987-04-01), Higuchi

Affiliated with

Also associated with

Rating

Semiconductor memory device having redundancy configuration with does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device having redundancy configuration with, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device having redundancy configuration with will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-467017