Boots – shoes – and leggings
Patent
1985-12-12
1988-11-08
Shaw, Gareth D.
Boots, shoes, and leggings
365189, G06F 1200, G11C 700
Patent
active
047837322
ABSTRACT:
A multiport memory includes first and second signal lines. Each signal line can simultaneously and independently access a particular address during a read memory portion of a clock pulse whereas both signal lines are used to write data to one address during another portion of the clock pulse.
REFERENCES:
patent: 3364472 (1968-01-01), Sloper
patent: 3906458 (1975-09-01), Ehleys
patent: 4092728 (1978-05-01), Baltzer
patent: 4150364 (1979-04-01), Baltzer
patent: 4228496 (1980-10-01), Katzman
patent: 4287563 (1981-09-01), Huston, Jr.
patent: 4541076 (1985-09-01), Bowers et al.
"A Study of Fault Tolerance Techniques for Associative Processors", National Computer Conference, 1974, pp. 643-652, by B. Parkami et al.
"An LSI Adaptive Array Processor", IEEE Journal of Solid State Circuits, Apr. 1983, pp. 147-155, by T. Kondo et al.
"Intel 8085A", from Microcomputer Hardware Handbook, .COPYRGT.1982, by Ing W. Hofacker GmbH, pp. 477-478.
"Motorola 6801", Microcomputer Hardware Handbook, .COPYRGT.1982, by Ing W. Hofacker, GmbH, pp. 353-354.
"Multiprocessing Technology", by Chian Linn Wu, Jun. 1985, IEEE Computer".
"Parallel Processing Gets Down to Business", by E. S. Lerner, Jul. '85, High Technology, pp. 20-28.
"Design of MPP", by K. E. Butcher, IEEE Computer Society, 1980, pp. 80 to 85.
Fitzgerald Joseph T.
ITT Corporation
Peterson T. L.
Shaw Gareth D.
LandOfFree
Two-wire/three-port RAM for cellular array processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Two-wire/three-port RAM for cellular array processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Two-wire/three-port RAM for cellular array processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-466397