Multichip integrated circuit packaging configuration and method

Details Multichip integrated circuit packaging configuration and method Multichip integrated circuit packaging configuration and method

Filed on

1986-09-26

Date issued

1988-11-08

Examiner

James, Andrew J.

Other Related Categories

357 67, 357 68, 357 71, H01L 2348

Type

Patent

Status

active

Patent number

047836954

Description

ABSTRACT:
A multichip integrated circuit package comprises a substrate to which is affixed one or more integrated circuit chips having interconnection pads. A polymer film overlying and bridging integrated circuit chips present is provided with a plurality of via openings to accommodate a layer of interconnection metallization which serves to connect various chips and chip pads within the interconnection pads disposed on the chips. A significant advantage of the packaging method and configuration of the present invention is the ability for the polymer film to be removed. This significantly improves testability and effectively provides wafer scale integration circuit packages which are free of problems associated with yield and testability.

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Auletta, L. V. et al., "Flexible Tape Conductor Interconnection for Chips", IMB Technical Disclosure Bulletin, vol. 24, No. 2, Jul. 1981, pp. 1214-1215.
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Lukaszek, W. et al., "CMOS Test Chip Design for Process Problem Debugging and Yield Prediction Experiments", Solid State Technology, Mar. 1986, pp. 87-93.

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