Semiconductor integrated circuit device constructed by polycell

Details Semiconductor integrated circuit device constructed by polycell Semiconductor integrated circuit device constructed by polycell

1985-11-08

1987-12-29

Edlow, Martin H.

357 45, 357 40, 357 59, H01L 2348, H01L 2710, H01L 2702

Patent

active

047164522

ABSTRACT:
A semiconductor integrated circuit device has cell arrays each constituted by unit cells containing functional circuits. Polysilicon wiring layers or diffusion wiring layers are formed in the wiring regions provided among the arrays. A first metal wiring layer is formed by computer-aided design above each polysilicon wiring layer or each diffusion wiring layer. An insulating layer is then formed on the first metal wiring layer. A second metal wiring layer is formed by computer-aided design above the insulating layer. A via contact hole is cut in the insulating layer. A portion of the second metal wiring layer fills up the via contact hole, whereby the second metal wiring layer is connected to the first metal wiring layer. The via contact hole is formed above each polysilicon wiring layer or each diffusion wiring layer. It may have its axis intersecting with the axis of the polysilicon or diffusion wiring layer or not intersecting therewith. In the first case, the overlapping portions of the first and second metal wiring layer are made broader to facilitate the forming of the via contact hole. In the second case, the portion of each polysilicon or diffusion wiring layer which is positioned below the via contact hole is made broader than the other portions.

REFERENCES:
patent: 3921282 (1975-11-01), Cummingham et al.
patent: 4161662 (1979-07-01), Malcolm et al.
patent: 4249193 (1981-02-01), Balyoz et al.
Patents Abstracts of Japan, vol. 2, No. 35, (E-77), Mar. 9, 1978, p. 12638 E 77, JP A 53 87, (Tokyo Shinaura), 5-1-78.
Shiotari et al., "New Taplas for Full Custom C2MOS LSI Design", IEEE CICC, pp. 111-114, 1982.

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