Disenabling circuit for power-on event

Details Disenabling circuit for power-on event Disenabling circuit for power-on event

1988-11-07

1990-08-14

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072723, 3072965, 307350, 307443, H03K 5153, H03K 1722, H03K 17284

Patent

active

049489950

ABSTRACT:
A disenabling circuit upon a power-on event comprises a level detecting circuit provided with a series combination of plural p-channel type load transistors and at least one n-channel type shifting transistor coupled between a positive power supplying line and a ground terminal, and a complementary inverter circuit coupled at an input node thereof to the output node of the level detecting circuit and having an output node where a disenabling signal of active high level is produced. The shifting transistor is responsive to the voltage level at the output node of the complementary inverter circuit, so that no conduction path takes place in the level shifting circuit after the disenabling signal recovers from the active level to the inactive low level.

REFERENCES:
patent: H497 (1988-07-01), Piasecki
patent: 4045688 (1977-08-01), Stewart
patent: 4633107 (1986-12-01), Norsworthy
patent: 4709165 (1987-11-01), Higuchi et al.
patent: 4716323 (1987-12-01), Wada et al.

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