Logical biMOS gate circuit having low power dissipation

Details Logical biMOS gate circuit having low power dissipation Logical biMOS gate circuit having low power dissipation

1985-09-30

1987-12-29

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307554, 307570, H03K 1716, H03K 1902, H03K 508, H03K 1760

Patent

active

047163100

ABSTRACT:
A logical gate circuit includes an emitter-grounded switching transistor and a pull-up circuit connected to a collector of the switching transistor. The switching transistor is cut OFF when an input signal has a high level and is turned ON when the input signal has a low level. A control MIS transistor is connected to a base of the switching transistor and is turned ON and OFF in response to respective low and high levels, of the output terminal of the switching transistor. An input transistor is connected in series with the control MIS transistor and is turned ON and OFF when the input signal is high and low, respectively. Thus, the logical gate circuit allows current to flow only during a transient signal period.

REFERENCES:
patent: 4425516 (1984-01-01), Wanlass

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