Process of fabricating a MISFET

Details Process of fabricating a MISFET Process of fabricating a MISFET

1989-11-01

1990-08-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437240, 148DIG106, 148DIG118, 357 233, H01L 21265

Patent

active

049487442

ABSTRACT:
In a process of fabricating a MISFET of the LDD structure, a gate insulation film is formed on a semiconductor substrate or a semiconductor thin film. A gate electrode is formed on the gate insulation film, and lightly-doped regions are formed in the semiconductor substrate or the semiconductor thin film by ion implantation using the gate electrode as a mask. Next, a CVD oxide film containing an impurity is unselectively deposited, sidewalls are formed along the edges of the gate electrodes by anisotropic etching, and heavily-doped source and drain regions are formed in the semiconductor substrate or the semiconductor thin film by ion implanation using the gate electrode and the sidewalls as a mask.

REFERENCES:
patent: 4597824 (1986-07-01), Shinada et al.
patent: 4637124 (1987-01-01), Okuyama et al.
patent: 4755479 (1988-07-01), Miura
Tsang et al., "Fabrication of High-Performance LDDFET's With Oxide Sidewall-Spacer Technology", IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 2, Apr. 1982, pp. 220-226.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1, Process Technology, Calif., Lattice Press, 1986, pp. 185-191.

Affiliated with

Also associated with

Rating

Process of fabricating a MISFET does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process of fabricating a MISFET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process of fabricating a MISFET will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-462709