Apparatus for handling register windows in an out-of-order proce

Details Apparatus for handling register windows in an out-of-order proce Apparatus for handling register windows in an out-of-order proce

1997-06-25

1999-08-24

De Cady, Albert

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712228, G06F 1500

Patent

active

059419776

ABSTRACT:
In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to physical addresses. The processor has a register window movable within a register file, a window pointer register maintaining a value corresponding to the location of the window in the register file, a speculative window pointer register maintaining a speculative value of the window pointer register. A controller identifies an instruction expected to modify the value in the window pointer register, and in response to identifying the instruction the controller modifies the speculative value. A mapper, coupled to the speculative window pointer register, converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.

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David L. Weaver/Tom Germond, The SPARC Architecture Manual, SPARC International, Inc., Version 9, 1994, pp. 29-60,79-85,214-215,239-240.

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