Multi-port internally cached DRAM system utilizing independent s

Details Multi-port internally cached DRAM system utilizing independent s Multi-port internally cached DRAM system utilizing independent s

1995-12-29

1998-08-25

Lee, Thomas C.

395822, 395446, 395432, G06F 1300, G06F 1320

Patent

active

057992096

ABSTRACT:
A novel low cost/high performance multi-port internally cached dynamic random access memory architecture called `AMPIC DRAM`, and consequentially a unique system architecture which eliminates current serious system bandwidth limitations, providing a means to transfer blocks of data internal to the chip, orders of magnitude faster than the traditional approach, and with the chip also interconnecting significantly higher numbers of resources with substantially enhanced performance and at notably lower cost through the use of a system configuration based on this novel architecture and working equally efficiently for both main memory functions and as graphics memory, thus providing a truly low cost, high performance unified memory architecture.

REFERENCES:
patent: 5442747 (1995-08-01), Chan et a.
patent: 5457654 (1995-10-01), McLaury
patent: 5490112 (1996-02-01), Hush et al.
patent: 5550961 (1996-08-01), Chimoto
patent: 5581773 (1996-12-01), Glover

Affiliated with

Also associated with

Rating

Multi-port internally cached DRAM system utilizing independent s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-port internally cached DRAM system utilizing independent s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-port internally cached DRAM system utilizing independent s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-45953