Interconnection arrangement for a gate array

Details Interconnection arrangement for a gate array Interconnection arrangement for a gate array

1989-08-16

1991-03-12

James, Andrew J.

357 41, 357 42, H01L 2710

Patent

active

049996983

ABSTRACT:
An improved carpeting gate array having a plurality of basic cells (9) each comprising an N channel MOS transistor (8) and a P channel MOS transistor (7) continuously arranged in row and column directions comprises a logic cell region (20) comprising a plurality of basic cells (9) continuously formed in a channel width direction (a direction intersecting with a direction in which their gate electrodes (4) of a plurality of N channel or P channel MOS transistors are continuously arranged spaced apart from each other), and an interconnection region (21) for providing interconnections to the logic cells (20) continuously formed in the channel width direction. The size in a width direction of the interconnection region is defined by the size in a channel length direction (a direction intersecting with the channel width direction) of the basic cells (9).

REFERENCES:
patent: 4651190 (1987-03-01), Suzuki et al.
patent: 4771327 (1988-09-01), Usui
patent: 4884118 (1989-11-01), Hui et al.
Blumberg et al., "A 640K Transistor Sea-Of-Gates 1.2.mu. Micron HCMOS Technology," Digest of Technical Papers IEEE International Solid-State Circuits Conference, Feb. 17, 1988, pp. 74-75.
Okabe et al., "A 400K-Transistor CMOS Sea-of-Gates Array with Continuous Track Allocation," IEEE Journal of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1280-1286.
I. Ohkura et al., "Gate Isolation--A Novel Basic Cell Configuration for CMOS Gate Arrays", IEEE (1982), pp. 307-310.
H. Fukuda et al., "A CMOS Pair-Transistor Array Masterslice", pp. 16-17.
R. Blumberg et al., "Aluminum Screen Gives Superior Power Distribution in a Sea-of-Gates Array" (1988), pp. 16-19.

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