Communications: electrical – Digital comparator systems
Patent
1995-09-13
1997-03-11
Wambach, Margaret Rose
Communications: electrical
Digital comparator systems
G06F 702
Patent
active
056105738
ABSTRACT:
A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential amplifier. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line by an incremental amount, thereby decreasing the bit line differential. The differential amplifier switches to indicate an error when the polarity of the differential voltage between the bit lines is reversed relative to the normal state. Any given single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage of the bit lines. However, if more than one hit line is asserted, then both bit lines are dominated by the activated complementary pull-up and pull-down devices, respectively, causing the bit line differential voltage to reverse polarity. In effect, the combined incremental change of voltage due to activation of two or more pull-up and pull-down devices is greater than the maximum voltage differential between the bit line signals asserted by the buffers. The differential error amplifier detects the reversal of polarity of the bit line differential voltage and asserts an error signal.
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LSI Logic Corporation
Wambach Margaret Rose
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