Priority order decomposing apparatus

Details Priority order decomposing apparatus Priority order decomposing apparatus

1988-05-25

1990-09-04

Shaw, Dale M.

Boots, shoes, and leggings

3408255, G06F 738

Patent

active

049549782

ABSTRACT:
A priority order decomposing apparatus converting binary data of a plurality of bits into data wherein "1"s other than "1" of the bit whose priority order is the highest are removed, a circuit for checking whether or not "1" exists is installed for each group of bits taken as a unit of converting process. When "1" exists, this is transmitted directly to the low-order-bit side to immediately set the lower-order bits to "0". This permits the operating speed to be made faster.

REFERENCES:
patent: 4064421 (1977-12-01), Gajski et al.
patent: 4420695 (1983-12-01), Fisher
patent: 4773033 (1988-09-01), Ikumi
patent: 4785421 (1988-11-01), Takahashi et al.
R. M. M. Oberman, Digital Circuits for Binary Arithmetic, John Wiley & Sons, New York, 1979, pp. 277-281.
"Logical Design by Means of LSI" (pp. 39-41), Shunji Okugawa (Mar. 25, 1987), Kyoritsu Shuppan Kabushiki Kaisha, publisher.

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