Controlled delay circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

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Details

327263, 327264, 327266, H03H 1126

Patent

active

056105460

ABSTRACT:
Delay circuit comprising a delay cell formed by a current source (I) connected between drain and source of two field-effect transistors (PO, NO) whose gates are connected to each other in order to constitute the input of the cell, and an inverter (INV) linked to one or other of the terminals of the current source (I) according to whether the delay is to affect the leading edge or the trailing edge of the signal to be delayed, a capacitor (C) for defining a delay time (Te) proportional to the power supply voltage and inversely proportional to the current (I) delivered by the current source, being connected between the input of the inverter (INV) and earth, characterized in that it furthermore comprises a circuit (Ci, Cu, S1, S3, AMPLO, P1) for regulating the current delivered by the current source in order to make it proportional to the power supply voltage of the circuit.

REFERENCES:
patent: 4617477 (1986-10-01), DePaolis, Jr.
patent: 4704547 (1987-11-01), Kirsch
patent: 4800304 (1989-01-01), Takeuchi
patent: 4967110 (1990-10-01), Matsuura
patent: 5066868 (1991-11-01), Doty, II et al.
patent: 5068553 (1991-11-01), Love
patent: 5117130 (1992-05-01), Shoji
patent: 5180938 (1993-01-01), Sin
patent: 5214320 (1993-05-01), Truong

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