Data processor with multiple register blocks

Details Data processor with multiple register blocks Data processor with multiple register blocks

1985-08-08

1988-03-22

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 906, G06F 1300

Patent

active

047333464

ABSTRACT:
A data processing apparatus includes a plurality of register blocks, each having a plurality of registers, an external memory either to save data in the register blocks or to restore data in the register blocks, and a data processing unit to execute a program using at least one of these register blocks. This data processing unit generates a first or a second signal when a subroutine call or a return occurs in the program being executed. The data processing apparatus further includes a memory interface to execute the data transfer between the register block set in the "save" or "restore" state and the external memory when the first or second signal is generated, and a register control for setting at least one of those register blocks in a state that can be used by the program executing means, and for setting a different register block into the "save" or "restore" state in response to the first or second signal.

REFERENCES:
patent: 4268901 (1981-05-01), Subrizi et al.
patent: 4298954 (1981-11-01), Bigelow et al.
patent: 4459657 (1984-07-01), Murao
patent: 4493020 (1985-01-01), Kim et al.
patent: 4530047 (1985-07-01), Rogers et al.
Paterson, et al., "A VLSI RISC", IEEE Computer, vol. 15, pp. 8-21 Sep. 1982.

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