Microprocessor circuits, systems, and methods passing intermedia

Details Microprocessor circuits, systems, and methods passing intermedia Microprocessor circuits, systems, and methods passing intermedia

1996-10-30

1998-08-25

Kim, Kenneth S.

395394, 395395, 39580023, G06F 938

Patent

active

057991804

ABSTRACT:
Circuits, systems, and methods relating to processor which processes a plurality of sequentially arranged instructions. In the method, one method step (10) receives into a processor pipeline an instruction from the plurality of sequentially arranged instructions. Another step (12) determines whether the received instruction comprises a short forward branch instruction. If the received instruction comprises a short forward branch instruction, the method (14) issues a detection signal and (16) issues a condition signal representing whether or not the condition of the short forward branch instruction is satisfied. Continuing, the method (18) receives into the processor pipeline a first group of instructions of the plurality of sequentially arranged instructions, where each is between the short forward branch instruction and the target instruction. Each such instruction passes fully through the processor pipeline and the method (26) suppresses its result in response to the detection signal if the condition signal represents that the condition of the short forward branch is satisfied.

REFERENCES:
patent: 5051896 (1991-09-01), Lee et al.
patent: 5606676 (1997-02-01), Grochowski et al.
patent: 5623615 (1997-04-01), Salem et al.
patent: 5634103 (1997-05-01), Dietz et al.

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