Low-power, noise-resistant read-only memory

Details Low-power, noise-resistant read-only memory Low-power, noise-resistant read-only memory

1988-11-14

1990-02-06

Popek, Joseph A.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

307449, G11C 800

Patent

active

048993158

ABSTRACT:
A low-power, noise-resistant, read-only memory (10) is comprised of a plurality of array sections (14), each section (14) having a plurality of cell locations (70-86) arranged in rows (98) and columns (88-96). Each column (88-96) is provided with a virtual ground line (107-114). Bit lines (116-126) are shared between columns (88-96). In operation, the bit lines (116-126) and virtual ground lines (107-114) are pulled up to a high voltage state. Then, one selected virtual ground line (107-114) in each section (14) is pulled low to address a pair of cell locations (70, 72) in that section (14). No active pullup means are employed. The transmission of false data through a sneak path (550) is prevented by the actuation of disconnect circuitry (38) after allowing all valid data to be sensed.

REFERENCES:
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3971001 (1976-07-01), Lodi

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