Boots – shoes – and leggings
Patent
1987-01-29
1990-02-06
Harkcom, Gary V.
Boots, shoes, and leggings
G06F 734, G06F 1535
Patent
active
048993018
ABSTRACT:
In a signal processor for processing zeroth through (N-1)-th input signal elements into zeroth through (N-1)-th output signal elements, the input elements are initially stored, as memorized data, in respective memory addresses of a memory arrangement (11, 12) by a memory accessing arrangement which comprises a first address calculating arrangement (311, 321) for calculating a first address for the memory addresses. A distance indicating arrangement (312, 322) is for indicating an address distance from the first address among the memory addresses. By using the first address and the address distance a second address is calculated by a second address calculating arrangement (313, 323). A pair of stored data are read from the first and the second addresses as a pair of read data. A calculation performing circuit (20) is for performing a predetermined calculation on the pair of read data by using a coefficient read from a read-only memory (14) to produce a pair of calculated data which are stored in the first and the second addresses as the stored data. The calculation performing circuit performs the predetermined calculation a plurality of times to produce the output elements.
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Kawakami Yuichi
Kuroda Ichiro
Nishitani Takao
Tanaka Hideo
Harkcom Gary V.
NEC Corporation
Shaw Dale M.
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