Patent
1989-04-20
1990-09-04
Larkins, William D.
357 234, 357 238, H01L 2940, H01L 2978
Patent
active
049548689
ABSTRACT:
A semiconductor component which comprises a planar structure which has a channel stopper 7 formed at one edge and a field electrode which covers a pn-junction 3 of the planar zones adjoining the edge 4. The blocking voltage can be increased by providing a channel stopper field plate 19 arranged over the channel stopper and an anode field plate 18 arranged over the field electrode and these field plates are spaced a greater distance from the surface 8 of the semiconductor body between the electrodes 18 and 19 and they have over the channel stopper electrode and the gate electrode.
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Claessen et al., `An Accurate DC Model for High Voltage Lateral DMOS Transistors Suited for CACD`, IEEE Trans on ED, vol. ED-33, Dec. 86.
Neilson et al, `Tapered Field`, RCA Tech Notes, 5-83.
Bergmann Rainer
Gantioler Josef-Matthias
Larkins William D.
Meier Stephen D.
Siemens Aktiengesellschaft
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