DMA controller performing data transfer by 2-bus cycle transfer

Details DMA controller performing data transfer by 2-bus cycle transfer DMA controller performing data transfer by 2-bus cycle transfer

1990-12-13

1994-03-22

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 36424231, 3642423, 364DIG2, G06F 1328

Patent

active

052972429

ABSTRACT:
A Direct Memory Access (DMA) controller (1) of a 2-bus cycle transfer type executes a read cycle first to fetch data from a data source then internally rearranges or aligns the fetched data in accordance with a bus width and/or a storing address of a data destination unit and thereafter executes a write cycle to write the rearranged data in the data destination unit. The DMA controller includes a data register (106) having first and second fields (106-1 and 106-2). Data from the data source is temporarily stored in one of the first and second fields of the data register during the read cycle, and data in the other of the first and second fields is written to the data destination unit during the write cycle.

REFERENCES:
patent: 4491909 (1985-01-01), Shimizu
patent: 4598362 (1986-07-01), Kinjo et al.
patent: 4912632 (1990-03-01), Gach et al.
patent: 4933846 (1990-06-01), Humphrey et al.
patent: 4987529 (1991-01-01), Craft et al.
patent: 5214767 (1993-05-01), Wanner et al.
M. Morris Manno, computer system architecture, 2nd edition, 1982, pp. 403-473.

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