Method and apparatus for deferred package assignment for compone

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364488, 364491, G06F 1546

Patent

active

052970531

ABSTRACT:
A computer aided design tool provides a user with the capability of generating a design implementation for electronic circuitry. In this system the user generates a design schematic specifying a functional description of a design for electronic circuitry without the need for specifying packaging information. The system is provided with a packaging tool for generating a physical package for the circuitry of the design schematic. Use of the packaging tool may be deferred until the design schematic has been completed and verified. Further, a user of the system has the option of specifying certain packaging information when creating the design schematic or delaying such specification until just prior to packaging of the design.

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patent: 5031111 (1991-07-01), Chao et al.
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patent: 5097422 (1992-03-01), Corbin, II et al.
patent: 5164908 (1992-11-01), Igarashi
patent: 5198987 (1993-03-01), Shindo et al.

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