Integrated circuit die with resistive substrate isolation of mul

Details Integrated circuit die with resistive substrate isolation of mul Integrated circuit die with resistive substrate isolation of mul

1988-02-29

1989-07-11

LaRoche, Eugene R.

357 51, 357 52, H01L 2702, H01L 2934

Patent

active

048476722

ABSTRACT:
An improved integrated circuit die with multiple circuits on the same substrate of semiconductor material is formed with circuit elements of the multiple circuits grouped respectively into at least first and second circuit areas or sections of the die. The first and second circuit sections of the die are separated and spaced from each other by a moat or separating boundary line. The separating boundary line is formed using appropriate mask lines on the fabrication masks. The separating boundary line is composed of the substrate semiconductor material between the circuit sections. The separating boundary line is formed without implanting buried collector layers or channel stop regions in the substrate semiconductor material of the boundary line width and depth. Relatively high resistive substrate isolation of the circuit sections of the die reduces feed through coupling of AC signal between circuit elements of the respective circuit sections. Separate substrate taps are provided for each circuit section fo the die and separate substrate tap leads are provided to each circuit section.

REFERENCES:
patent: 3688132 (1972-08-01), Gill et al.
patent: 4298881 (1981-11-01), Sakurada
patent: 4321616 (1982-03-01), Bise
patent: 4498227 (1985-02-01), Howell et al.

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