Semiconductor memory device having two-dimensional matrix array

Details Semiconductor memory device having two-dimensional matrix array Semiconductor memory device having two-dimensional matrix array

1989-07-21

1991-07-23

Popek, Joseph A.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, G11C 800

Patent

active

050349287

ABSTRACT:
A semiconductor memory device has a memory cell matrix in which a plurality of memory cells are connected in rows by work lines and in columns by bit lines. The device comprises cell row groups each of which is formed by memory cell rows commonly activated by several row address signals at a first selection stage, a row group selection decoder having the smallest decoding circuits as a first stage decoder each connected to the row group(s) by first stage word line and commonly activating any group(s) at the first row selection stage by several row address signals, and a row selection decoder as a second stage decoder having the smallest decoding units entirely provided in the matrix and each activating any cell row(s) at a second selection stage by remaining row address signals.

REFERENCES:
patent: 4429374 (1984-01-01), Tanimura
patent: 4597064 (1986-06-01), Giebel

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