Thin decoupling capacitor for mounting under integrated circuit

Electricity: electrical systems and devices – Electrostatic capacitors – Fixed capacitor

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361321, H01G 114, H01G 410

Patent

active

050348507

ABSTRACT:
A rugged, highly reliable, leadless decoupling capacitor is provided which may be positioned between a circuit board and an integrated circuit package including, for example, a leaded surface mounted IC package or Pin Grid Array package. This decoupling capacitor is comprised of a rugged ceramic or like substrate having printed or otherwise applied thereon a very thin high capacitance layer made by thick or thin film processes which is sandwiched between two thin electrode layers. Conductive castellations extend from the electrode layers along the surface of the ceramic substrate for connection to the circuit board. Preferably, an electrically insulative protective layer encapsulates the capacitor. The dielectric layer preferably comprises a high dielectric glass/ceramic dielectric paste or dielectric sol-gel layer. The overall thickness of the decoupling capacitor may be less than 0.020 inch.

REFERENCES:
patent: 2972570 (1961-02-01), Haas et al.
patent: 4665465 (1987-05-01), Tanabe
patent: 4734819 (1988-03-01), Hernandez et al.
patent: 4868711 (1989-09-01), Hirama et al.

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