Method for manufacturing an EPROM cell

Fishing – trapping – and vermin destroying

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437 49, H01L 21265

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active

052963977

ABSTRACT:
Disclosed is a floating gate EPROM cell wherein a trench is formed in and divides the semiconductor substrate into two portions. Separated source and drain regions are formed in one portion and contact one side of the trench region, and a control gate region is formed in the second portion and contacts the opposite side of the trench. A first insulating film covers the source, drain, trench regions and part of the control gate region, a portion of which is covered by a first polycrystalline silicon film which forms the floating gate. A second insulating layer covers the first polycrystalline silicon film and also a portion of the control gate region, which, in turn, is covered by a second polycrystalline silicon layer which extends beyond the second insulating layer into electrical contact with the control gate region. Thus, a control gate is provided both above and below the floating gate. The coupling efficiency between the control gate and the floating gate is primarily determined by the thickness of the first insulating film, which allows the second insulating film to be thicker to insure against current leakage from the floating gate and at the same time easier to deposit.

REFERENCES:
patent: 4668970 (1987-05-01), Yatsuda et al.
patent: 4698900 (1987-10-01), Esquivel
patent: 4855800 (1989-08-01), Esquivel et al.
patent: 5045490 (1991-09-01), Esquivel et al.
patent: 5049515 (1991-09-01), Tzeng
patent: 5087584 (1992-02-01), Wada et al.
patent: 5100818 (1992-03-01), Arima et al.
"A Novel Trench-Isolated Buried N.sup.+ FAMOS Transistor Suitable for High-Density EPROM's " by A. L. Esquivel et al.; pp. 146-147, 8179 I.E.E.E. Electron Device Letters EDL-Apr. 8, 1987, No. 4, New York, U.S.A.
International Electron Devices Meeting Dec. 7-10, 1986, Los Angeles, Calif.; Sponsored by Electron Devices Society of I.E.E.E. pp. 592-595.
A High-Speed 1-Mbit EPROM with a Ti-Silicided Gate by Y. Narita et al. I.E.E.E. Journal of Solid-State Circuits, vol. SC-20, No. 1, Feb. 1985, pp. 418-421.
"Technology of a New n-Channel One-Transistor EAROM Cell Called SIMOS" by A. Scheibe et al. I.E.E.E. Transactions on Electron Devices, vol. ED-24, No. 5, May 1977, pp. 600-610.

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