Fishing – trapping – and vermin destroying
Patent
1992-08-03
1994-03-22
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 52, 437 56, 437 57, H01L 21265
Patent
active
052963934
ABSTRACT:
An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (139/140); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (141, 142) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (143); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (144, 145); vertical and lateral annular DMOS transistors (146, 147); a Schottky diode (148); and a FAMOS EPROM cell (149). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.
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Falessi Georges
Hutter Louis
Smayling Michael C.
Todd James R.
Torreno Manuel
Donaldson Richard L.
Hearn Brian E.
Holland Robby T.
Nguyen Tuan
Texas Instruments Incorporated
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