Method of fabricating a high voltage semiconductor device having

Details Method of fabricating a high voltage semiconductor device having Method of fabricating a high voltage semiconductor device having

1987-02-26

1988-11-22

Ozaki, George T.

Fishing, trapping, and vermin destroying

437 66, 437 68, H01L 2138

Patent

active

047866144

ABSTRACT:
A method of fabricating a semiconductor device capable of handling high voltages includes forming a relatively thick epitaxial layer the top surface of which defines a plurality of generally V-shaped grooves, a pair of the grooves having formed therebetween active device regions, such pair of grooves acting as isolation regions including impurity regions extending on both sides of the groove through the epitaxial layer to a lower layer. A pair of grooves formed inward of the first-mentioned grooves contact active regions of the device into which the V-shaped portions extend, again with each such V-shaped portion having impurity regions extending on both sides thereof. The impurity regions associated with the V-shaped grooves are formed simultaneously with other active regions of the device.

REFERENCES:
patent: 3847687 (1974-11-01), Davidsohn
patent: 3920482 (1975-11-01), Russell
patent: 4255207 (1981-03-01), Nicolay et al.
patent: 4269636 (1981-05-01), Rivoli et al.
patent: 4682405 (1987-07-01), Blanchard et al.

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