Method of coplanar integration of semiconductor IC devices

Details Method of coplanar integration of semiconductor IC devices Method of coplanar integration of semiconductor IC devices

1990-09-12

1991-12-24

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437211, 437 51, 437208, 437915, 437 90, 357 75, H01L 2504

Patent

active

050752537

ABSTRACT:
A high degree of wafer-scale integration of normally incompatible IC devices is achieved by providing a plurality of segments (10), each segment having thereon one or more circuits, circuit elements, sensors and/or I/O connections (14'). Each segment is provided with at least one edge (12) having an abutting portion (12a) capable of abutting against a similar edge of a neighboring segment. The segments are placed on the surface of a flotation liquid (20) and are allowed to be pulled together so as to mate abutting edges of neighboring segments, thereby forming superchips (10'). Microbridges (22) are formed between neighboring segments, such as by solidifying the flotation liquid, and interconnections (26) are formed between neighboring segments. In this manner, coplanar integration of semiconductor ICs is obtained, permitting mixed and normally incompatible circuit functions on one pseudomonolithic device as diverse as silicon and III-V digital circuits, III-V optoelectronic devices, static RAMs, charge coupled devices, III-V lasers, superconducting thin films, ferromagnetic non-volatile memories, high electron mobility transistors, and bubble memories, to name a few, to be integrated in any desired combination. The yieldable scale of integration of a given device technology is also greatly extended. The segments are brought together in a particulate-free fashion with high throughput and exacting reproducibility at low cost.

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