Patent
1997-02-28
1999-03-02
Heckler, Thomas M.
39575004, G06F 104, G06F 132
Patent
active
058782516
ABSTRACT:
In the interval stop clock mode, the stop clock generating circuit in the system controller generates a stop clock signal that alternates between the active state and the inactive state and supplies the signal to the CPU. This causes the CPU to alternate between a state where the CPU is stopped from executing an instruction and an instruction executable state. In such a computer system, an interrupt type sensing circuit senses various interrupt request signals generated in the system and determines the type of each interrupt request. A stop clock temporary stopping circuit controls the stop clock generating circuit so as to bring the stop clock signal in the inactive state for the period of time specified by the timer value stored in the register corresponding to the determined type of the interrupt request. With this configuration, the performance of the CPU is prevented from falling off in a case where a load is exerted on the CPU as a result of a hardware interrupt to the CPU having occurred in the interval stop clock mode.
REFERENCES:
patent: 4748559 (1988-05-01), Smith et al.
patent: 4851987 (1989-07-01), Day
patent: 5025387 (1991-06-01), Franc
patent: 5546568 (1996-08-01), Bland et al.
patent: 5692197 (1997-11-01), Narad et al.
Hagiwara Yuko
Matoba Tsukasa
Heckler Thomas M.
Kabushiki Kaisha Toshiba
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