Method of designing semiconductor device including density...

Details Method of designing semiconductor device including density... Method of designing semiconductor device including density...

2009-09-09

2011-12-13

Garbowski, Leigh (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Design of semiconductor mask or reticle

Analysis and verification

C716S111000, C716S136000

Reexamination Certificate

active

08078994

ABSTRACT:
A method of designing a semiconductor device includes density verification of layout data of the semiconductor device at a macro level. The method includes disposing virtual patterns each including a predetermined step width on a circumference of a verification frame; and moving the verification frame outside which the virtual patterns are disposed sequentially by the predetermined step width and performing the density verification of the layout data of the semiconductor device.

REFERENCES:
patent: 6505325 (2003-01-01), Hamamoto
patent: 7093212 (2006-08-01), DeCamp et al.
patent: 7269807 (2007-09-01), Shimada et al.
patent: 7343580 (2008-03-01), Zorrilla et al.
patent: 2005/0204327 (2005-09-01), Mukai et al.
patent: 6-125007 (1994-05-01), None
patent: 2001-60212 (2001-03-01), None
patent: 2003-67441 (2003-03-01), None
patent: 2005-222214 (2005-08-01), None
International Search Report for PCT/JP2007/055558, mailed Apr. 17, 2007.

Affiliated with

Also associated with

Rating

Method of designing semiconductor device including density... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of designing semiconductor device including density..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of designing semiconductor device including density... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4312306