Data processing: structural design – modeling – simulation – and em – Emulation – Of instruction
Reexamination Certificate
2008-12-09
2011-11-15
Rodriguez, Paul (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Of instruction
C703S023000, C717S138000
Reexamination Certificate
active
08060356
ABSTRACT:
Processor emulation using fragment level translation is disclosed. A target system having a main target processor, a secondary target processor element and an instruction memory associated with the secondary target processor element may be emulated with a host system having one or more host processors and a host memory. Two or more target system code instructions for the secondary target processor may be grouped into one or more fragments with known starts and ends. A data structure that maps the host memory locations of the starts and ends may be maintained. Each fragment may be translated into a corresponding set of position-independent translated fragments executable by the host system. The translated fragments may be loaded into one or more of the host processors. If a memory layout for target system code corresponding to the one or more fragments has changed, the fragments may be dynamically re-linked, without re-translation, and executed.
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Isenberg Joshua D.
JDI Patent
Johnson Cedric D
Rodriguez Paul
Sony Computer Entertainment Inc.
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