Semiconductor memory device with a stacked gate including a...

Details Semiconductor memory device with a stacked gate including a... Semiconductor memory device with a stacked gate including a...

2009-03-18

2011-12-13

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185260, C365S185250, C365S189090, C365S189110, C365S230060

Reexamination Certificate

active

08077523

ABSTRACT:
A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

REFERENCES:
patent: 7085162 (2006-08-01), Nakamura et al.
patent: 7274603 (2007-09-01), Futatsuyama et al.
patent: 7286402 (2007-10-01), Nakamura et al.
patent: 2002-63795 (2002-02-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device with a stacked gate including a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with a stacked gate including a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with a stacked gate including a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4307717