Method and system for mitigating risk of electrostatic...

Details Method and system for mitigating risk of electrostatic... Method and system for mitigating risk of electrostatic...

2008-11-05

2011-12-13

Salce, Patrick (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S220000, C361S781000, C361S799000

Reexamination Certificate

active

08077439

ABSTRACT:
Aspects of a method and system for mitigating risk of electrostatic discharge in a system on chip are provided. In this regard, for an IC comprising a plurality of portions electrically isolated from one another within the IC, ESD current may be routed via one or more paths within and/or on a package to which the IC is bonded. The one or more paths may electrically couple two or more of the portions of the IC. The one or more paths may have low impedance at DC and high impedance at one or more frequencies utilized in the integrated circuit. One of the portions of the IC may be a ground plane for RF circuitry. One of the portions of the IC may be a ground plane for digital circuitry. The one or more paths may be fabricated in one or more metal layers of said package.

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