Sense amplifier circuit and semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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Details

C365S196000, C365S207000

Reexamination Certificate

active

08068369

ABSTRACT:
A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell.

REFERENCES:
patent: 6154402 (2000-11-01), Akita
patent: 6314028 (2001-11-01), Kono
patent: 2002/0060924 (2002-05-01), Ito
patent: 2009/0175066 (2009-07-01), Kim
patent: 11-16384 (1999-01-01), None
patent: 2000-195268 (2000-07-01), None
patent: 2002-157885 (2002-05-01), None
patent: 2007-73121 (2007-03-01), None

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