Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2008-07-21
2011-12-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
C716S104000
Reexamination Certificate
active
08086974
ABSTRACT:
In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. A method in a computer-aided design system for generating a functional design model of a fractional-N phased-lock-loop (PLL) structure is provided in one embodiment. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit is presented in another embodiment.
REFERENCES:
patent: 1957752 (1934-05-01), Avery
patent: 3739270 (1973-06-01), Miller et al.
patent: 4087757 (1978-05-01), Cunningham
patent: 4363138 (1982-12-01), Franklin et al.
patent: 5032839 (1991-07-01), Even-Or
patent: 5041745 (1991-08-01), Raso
patent: 5909661 (1999-06-01), Abramovitch et al.
patent: 6008821 (1999-12-01), Bright et al.
patent: 6298046 (2001-10-01), Thiele
patent: 6327542 (2001-12-01), McBride
patent: 6388480 (2002-05-01), Stubbs et al.
patent: 6404276 (2002-06-01), Liu
patent: 6686809 (2004-02-01), Nystrom et al.
patent: 6724846 (2004-04-01), Lo
patent: 6813484 (2004-11-01), Tolson
patent: 6842069 (2005-01-01), Takahashi et al.
patent: 6915503 (2005-07-01), Lesea
patent: 7005899 (2006-02-01), Fallahi et al.
patent: 7120412 (2006-10-01), Anand
patent: 7181711 (2007-02-01), Foreman et al.
patent: 7183860 (2007-02-01), Staszewski et al.
patent: 7288998 (2007-10-01), Thomsen et al.
patent: 7292947 (2007-11-01), Tabatabaei
patent: 7295077 (2007-11-01), Thomsen et al.
patent: 7310593 (2007-12-01), Hammerschmidt
patent: 7313176 (2007-12-01), Groen
patent: 7321847 (2008-01-01), Welkie et al.
patent: 7365580 (2008-04-01), Martin et al.
patent: 7750697 (2010-07-01), Feng
patent: 7926015 (2011-04-01), Feng
patent: 2003/0224747 (2003-12-01), Anand
patent: 2004/0210790 (2004-10-01), Moon et al.
patent: 2005/0107970 (2005-05-01), Franch et al.
patent: 2005/0111536 (2005-05-01), Cranford et al.
patent: 2005/0186920 (2005-08-01), Staszewski et al.
patent: 2005/0246142 (2005-11-01), Hammerschmidt
patent: 2006/0033582 (2006-02-01), Staszewski et al.
patent: 2006/0202714 (2006-09-01), Hoang et al.
patent: 2006/0245531 (2006-11-01), Leonowich et al.
patent: 2006/0248485 (2006-11-01), Foreman et al.
patent: 2007/0100596 (2007-05-01), Hollis
patent: 2007/0103240 (2007-05-01), Staszewski et al.
patent: 2007/0152762 (2007-07-01), Hung et al.
patent: 2007/0205833 (2007-09-01), Mar et al.
patent: 2007/0233444 (2007-10-01), O'Mahony et al.
patent: 2009/0015304 (2009-01-01), Yin et al.
patent: 2009/0096497 (2009-04-01), Feng
patent: 2009/0212835 (2009-08-01), Xu et al.
patent: 2009/0243674 (2009-10-01), Feng
patent: 2009/0243675 (2009-10-01), Feng
patent: 04234211 (1992-08-01), None
Final Office Action Summary from U.S. Appl. No. 12/176,500 mailed on Dec. 7, 2009.
Notice of Allowance from U.S. Appl. No. 12/176,500 mailed on Feb. 25, 2010.
Kim, “A Fractional-N-PLL Frequency Synthesizer Design” 2005 IEEE.
Wang, “A Generic Multi-Modulus Divider Architecture for Fractional-N Frequency Synthesisers” 2007 IEEE.
Notice of Allowance from U.S. Appl. No. 12/060,162 mailed on Jul. 10, 2008.
Office Action Summary from U.S. Appl. No. 12/176,500 mailed on Sep. 17, 2009.
International Business Machines - Corporation
Siek Vuthe
Zilka-Kotab, PC
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