Chip packaging with metal frame pin grid array

Details Chip packaging with metal frame pin grid array Chip packaging with metal frame pin grid array

2009-06-08

2011-10-11

Estrada, Michelle (Department: 2829)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S112000, C438S127000, C257SE23024, C257SE23001, C257SE21499

Reexamination Certificate

active

08034657

ABSTRACT:
A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place.

REFERENCES:
patent: 6130116 (2000-10-01), Smith et al.

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