Single chip controller-memory device and a memory architecture a

Details Single chip controller-memory device and a memory architecture a Single chip controller-memory device and a memory architecture a

1995-11-01

1996-12-10

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 345188, G11C 800, G06F 1520

Patent

active

055838227

ABSTRACT:
A method is provided for operating a memory including a plurality of blocks of memory cells and a plurality of address decoders, each address decoder allowing access to selected cells in a corresponding one of the blocks in response to selected row and column address bits presented substantially simultaneously on an associated address bus. A first set of row and column address bits are presented on the address bus to access selected cells in a first selected one of the blocks via an associated data bus coupled to each of the blocks. A second set of row and column address bits are then presented on the address bus to access selected cells in a second selected one of the blocks via the data bus.

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