Method and apparatus for adjustment and control of an iterative

Static information storage and retrieval – Floating gate – Particular biasing

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365 45, G11C 1604

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active

058779841

ABSTRACT:
A circuit and method for adjusting the ramp voltage applied to a control gate of a non-volatile memory cell to improve programming accuracy. The method involves measuring an amount of additional voltage realized at a source of the floating gate transistor. Thereafter, a preset compensation ratio may be selected to reduce a ramp voltage applied to the control gate of the memory cell by an amount necessary to lessen the amount of additional voltage realized at the source of the floating gate transistor. This will reduce inaccurate measurement of voltages during the read-while-write voltage program technique. A voltage control circuit is connected to the control gate for precise reduction of the ramp voltage.

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