Systems and methods for ASIC power consumption reduction

Details Systems and methods for ASIC power consumption reduction Systems and methods for ASIC power consumption reduction

2007-06-29

2011-11-01

DeCady, Albert (Department: 2121)

Data processing: generic control systems or specific application

Generic control system, apparatus or process

Specific compensation or stabilization feature

C700S126000, C713S300000, C713S320000, C702S096000, C702S107000, C702S176000

Reexamination Certificate

active

08050781

ABSTRACT:
Embodiments of the present invention are directed to dynamically measuring the speed of a circuit and modifying the operating voltage of the circuit based on the measured speed, in order to minimize the power being used while still ensuring proper operation of the circuit. Consequently, circuits of higher inherent speeds may have their voltages decreased (thus decreasing their actual speeds), while circuits of lower speeds may have their voltages increased, or kept the same. Thus, the resulting speeds of all circuits may be kept within a limited range to ensure proper operation. In addition, the power dissipated of circuits of higher speeds may be decreased.

REFERENCES:
patent: 4375614 (1983-03-01), Steiner
patent: 5461649 (1995-10-01), Bailey et al.
patent: 5920708 (1999-07-01), Gates et al.
patent: 6075389 (2000-06-01), Umemoto et al.
patent: 6366157 (2002-04-01), Abdesselem et al.
patent: 6381688 (2002-04-01), Gates et al.
patent: 7036029 (2006-04-01), May et al.
patent: 7075276 (2006-07-01), Morales
patent: 7137017 (2006-11-01), Itoh
patent: 2002/0120878 (2002-08-01), Lapidus
patent: 2004/0199821 (2004-10-01), Flautner et al.
patent: 2004/0268165 (2004-12-01), May et al.
patent: 2005/0001600 (2005-01-01), Morales
patent: 2005/0229056 (2005-10-01), Rohrbaugh et al.
patent: 2006/0071657 (2006-04-01), Emmert et al.
patent: 2006/0076973 (2006-04-01), Furukawa
patent: 2007/0057715 (2007-03-01), Yeh et al.
patent: 2007/0214377 (2007-09-01), Jarrar et al.
patent: 2007/0220388 (2007-09-01), Quereshi et al.

Affiliated with

Also associated with

Rating

Systems and methods for ASIC power consumption reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systems and methods for ASIC power consumption reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for ASIC power consumption reduction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4288016