Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes
Patent
1987-09-28
1989-06-06
Shoop, Jr., William M.
Coded data generation or conversion
Digital code to digital code converters
To or from variable length codes
341 55, 341 61, H03M 740
Patent
active
048375713
ABSTRACT:
The described circuit arrangement for converting a data signal having a constant bit rate and code words of different length into an output signal consisting of code words of constant length but with a variable bit rate while using a buffer memory comprises a first encoder which recognizes code words of the data signal and converts them into code words of equal length, said code words being written in the buffer memory, read out from this memory by a second encoder and being converted into code words of the output signal. The construction of the first encoder is characterized in that a first EPROM and a comparator are connected to the parallel outputs of a shift register through which the data signal with its bit clock is shifted. The output data of the first EPROM and of the comparator are transferred to an intermediate memory and simultaneously applied to the address inputs of a second EPROM. Among the outputs of the second EPROM there is an output at which pulses for the transfer of the output data of the first EPROM and of the comparator in the intermediate memory are present. The second EPROM generates erasing pulses for a counter whose stages are connected to inputs of the second EPROM. Among the output data of the second EPROM there are control signals with which logic circuits are controlled which convert the control signals into code words of equal length and pass them on to the buffer memory.
Barschall Anne E.
Blum Richard K.
Briody Thomas A.
Haken Jack E.
Shoop Jr. William M.
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