Method, system and application for sequential cofactor-based...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing

Reexamination Certificate

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C716S108000, C716S132000

Reexamination Certificate

active

08042075

ABSTRACT:
Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement.

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Michael L. Case et al., “Merging Nodes Under Sequential Observability” Annual ACM IEEE Design Automation Conference archive Proceedings of the 45th annual conference on Design automation table of contents Anaheim, California, Published 2008.

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