Ion implantation for suppression of defects in annealed SiGe...

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

Reexamination Certificate

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C257S190000, C257S616000, C257S617000, C257SE29104, C257SE29085

Reexamination Certificate

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08053759

ABSTRACT:
A substrate material including a Si-containing substrate and an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate. The substrate material further includes a substantially relaxed SiGe alloy layer present atop the insulating region, wherein the substantially relaxed SiGe alloy layer has a planar defect density from about 5000 defects/cm−2or less. The substrate material may be employed in a heterostructure, in which a strained Si layer is present atop the substantially relaxed SiGe alloy layer of the substrate material.

REFERENCES:
patent: 7164187 (2007-01-01), Nagasawa
patent: 2002/0185686 (2002-12-01), Christiansen et al.
patent: 2005/0054175 (2005-03-01), Bauer
patent: 2005/0151134 (2005-07-01), Hsu et al.
J. Cai, et al., “Strain relaxation and threading dislocation density in helium-implanted and annealed Si1-xlSi(100) heterostructures” Journal of Applied Physics, vol. 95, No. 10, May 15, 2004, pp. 5347-5351.
J. Cai et al., “Influence of He implantation conditions on strain relaxation and threading dislocation density in Si0.2virtual substrates”, Mat. Res. Soc. Symp. Proc. vol. 809 (2004).

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