Clock model for formal verification of a digital circuit...

Details Clock model for formal verification of a digital circuit... Clock model for formal verification of a digital circuit...

2008-12-23

2011-11-15

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S108000

Reexamination Certificate

active

08060847

ABSTRACT:
An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured states and associated attributes are used in formal verification of the circuit description. This approach helps to reduce or eliminate inaccuracies and other issues with other clock models such as a phase clock model. In one embodiment, a phase clock model can be used in addition to the edge clock model. In another embodiment, the edge clock states can be used to generate states according to different clock models, such as the phase clock model.

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Pgeifer et al. “Formal Verification for Time-Triggered Clock Synchronization”, Dependable Computing for Critital Applications 7, 1999, pp. 207-226.

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