Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-12-30
2011-12-13
Vicary, Keith (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
08078836
ABSTRACT:
In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions of multiple data elements. Sets of data elements are selected from corresponding portions of every lane of the source operand according to per-lane control bits. Elements of these sets are copied to specified fields in corresponding portions of every lane of the destination operand. Another embodiment of the shuffle instruction also specifies a second source operand, all operands having corresponding lanes divided into multiple data elements. A set selected according to per-lane control bits contains data elements from every lane portion of a first source operand and data elements from every corresponding lane portion of the second source operand. Set elements are copied to specified fields in every lane of the destination operand.
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Eitan Benny
Orenstein Doron
Sperber Zeev
Valentine Robert
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Vicary Keith
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