Overlay mark

Details Overlay mark Overlay mark

2011-03-21

2011-11-01

Smith, Zandra (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S048000, C257SE23179, C438S401000, C438S692000, C438S710000, C438S720000, C438S700000

Reexamination Certificate

active

08049345

ABSTRACT:
An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape.

REFERENCES:
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5747375 (1998-05-01), Kaneko et al.
patent: 5919714 (1999-07-01), Chen et al.
patent: 6118185 (2000-09-01), Chen et al.
patent: 7449792 (2008-11-01), Yang et al.
patent: 2005/0276465 (2005-12-01), Chen

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