Circuit for memory module

Details Circuit for memory module Circuit for memory module

2011-02-22

2011-12-20

Sofocleous, Alexander (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S051000, C365S149000, C365S230030, C365S233130, C711S105000, C711S115000

Reexamination Certificate

active

08081536

ABSTRACT:
A circuit is configured to be mounted on a memory module configured to be operationally coupled to a computer system. The memory module has a first number of ranks of double-data-rate (DDR) memory circuits activated by a first number of chip-select signals. The circuit is configurable to receive a set of signals comprising address signals and a second number of chip-select signals smaller than the first number of chip-select signals. The circuit is further configurable to generate phase-locked clock signals, to selectively isolate a load of at least one rank of the first number of ranks from the computer system in response at least in part to the set of signals, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

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