Implementation of wide multiplexers in reconfigurable logic

Details Implementation of wide multiplexers in reconfigurable logic Implementation of wide multiplexers in reconfigurable logic

2003-03-17

2011-12-20

Do, Chat C (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

08082284

ABSTRACT:
A reconfigurable processing device comprises one or more reconfigurable processing units. At least one processing unit utilizes a computational unit having a preprocessing module for receiving n input signals, and s1 selection signals, and providing k output signals wherein k<n+s1. The computational unit further comprises an m-output look-up table being addressed by the k output signals of the preprocessing module and an output multiplexer for selecting one of the m output signals of the look-up table under control of s2 further selection signals.

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