Multiple level programming in a non-volatile memory device

Details Multiple level programming in a non-volatile memory device Multiple level programming in a non-volatile memory device

Filed on

2008-05-22

Date issued

2011-10-25

Examiner

Zarabian, Amir (Department: 2827)

Patent Class

Static information storage and retrieval

SubClass

Floating gate

SubSubClass

Particular biasing

Other Related Categories

C365S185180, C365S185170, C365S185230, C365S185280

Type

Reexamination Certificate

Status

active

Patent number

08045392

Description

ABSTRACT:
The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.

REFERENCES:
patent: 6058042 (2000-05-01), Nobukata
patent: 6147910 (2000-11-01), Hsu
patent: 6181604 (2001-01-01), Lu
patent: 6538923 (2003-03-01), Parker
patent: 6771537 (2004-08-01), Jyouno et al.
patent: 6845060 (2005-01-01), Lee
patent: 7110300 (2006-09-01), Visconti
patent: 7450433 (2008-11-01), Wan et al.
patent: 2005/0248992 (2005-11-01), Hwang

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