Sharing logic circuitry for a maximum likelihood MIMO...

Details Sharing logic circuitry for a maximum likelihood MIMO... Sharing logic circuitry for a maximum likelihood MIMO...

2008-08-06

2011-11-15

Wang, Ted (Department: 2611)

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

C375S262000, C375S316000, C375S324000, C375S340000, C375S341000

Reexamination Certificate

active

08059745

ABSTRACT:
A receiver system for receiving and decoding modulated communications signals in a multiple-input, multiple-output (MIMO) environment, where the signals are modulated according to Orthogonal Frequency Division Modulation (OFDM). The receiver system includes shared decoder logic circuitry that executes a maximum-likelihood (ML) estimation algorithm in deriving the signals transmitted from the multiple transmitting antennae, as those signals were received over all of the receiving antennae. For a control channel portion of the data frame, the shared decoder logic circuitry applies Viterbi decoding to the transmitted datastreams estimated by the ML estimation algorithm. This sharing of decoder logic reduces the integrated circuit chip area, and also power dissipation, otherwise required in performing these complex decoding functions.

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