Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2009-05-29
2011-10-25
Luu, Chuong A. (Department: 2892)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S463000, C438S057000, C438S667000, C438S308000
Reexamination Certificate
active
08043940
ABSTRACT:
An improved yield of chips is realized by reducing the width of dicing streets on the front surface side of a semiconductor wafer. A method for semiconductor chip, divided a semiconductor wafer10having a plurality of circuit patterns formed on one surface18into pieces, comprising, forming a groove in a boundary region between the circuit patterns from the other surface19of the semiconductor wafer10by using a blade, forming a modified layer14in the boundary region between the circuit patterns by irradiation with laser light L from the one surface18or the other surface 19 of the semiconductor wafer10, and dividing the semiconductor wafer into pieces by breaking the modified layer14. The modified layer14is formed between a bottom surface17of a groove portion16and the one surface18of the semiconductor wafer10, and a forming width WM of the modified layer14is smaller than the width of the groove portion16.
REFERENCES:
patent: 2007/0105345 (2007-05-01), Kurosawa
patent: 6-232255 (1994-08-01), None
patent: 2006-222359 (2006-08-01), None
Luu Chuong A.
McGinn IP Law Group PLLC
Renesas Electronics Corporation
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